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G12648 - 74S373N Octal D-Type Transparent Latch
These 8-bit registers feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. The high-impedance 3-state and increased high-logic-level drive provide these registers with the capability of being connected directly to and driving the bus lines in a bus-organized system without need for interface or pullup components. These devices are particularly attractive for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.
The eight latches of the 74S373N are transparent D-type latches, meaning that while the enable (C or CLK) input is high, the Q outputs follow the data (D) inputs. When C or CLK is taken low, the output is latched at the level of the data that was set up.
Schmitt-trigger buffered inputs at the enable/clock lines of the 74S373N devices simplify system design as ac and dc noise rejection is improved by typically 400 mV due to the input hysteresis. A buffered output-control (OC) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly.OC\ does not affect the internal operation of the latches or flip-flops. That is, the old data can be retained or new data can be entered, even while the outputs are off.
Features:
Choice of Eight Latches or Eight D-Type Flip-Flops in a Single Package
3-State Bus-Driving Outputs
Full Parallel Access for Loading
Buffered Control Inputs
Clock-Enable Input Has Hysteresis to Improve Noise Rejection
P-N-P Inputs Reduce DC Loading on Data Lines
20 pin DIP. Actual brand may vary from picture.
G12648
The eight latches of the 74S373N are transparent D-type latches, meaning that while the enable (C or CLK) input is high, the Q outputs follow the data (D) inputs. When C or CLK is taken low, the output is latched at the level of the data that was set up.
Schmitt-trigger buffered inputs at the enable/clock lines of the 74S373N devices simplify system design as ac and dc noise rejection is improved by typically 400 mV due to the input hysteresis. A buffered output-control (OC) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly.OC\ does not affect the internal operation of the latches or flip-flops. That is, the old data can be retained or new data can be entered, even while the outputs are off.
Features:
Choice of Eight Latches or Eight D-Type Flip-Flops in a Single Package
3-State Bus-Driving Outputs
Full Parallel Access for Loading
Buffered Control Inputs
Clock-Enable Input Has Hysteresis to Improve Noise Rejection
P-N-P Inputs Reduce DC Loading on Data Lines
20 pin DIP. Actual brand may vary from picture.
G12648
$0.28
Original: $0.79
-65%G12648 - 74S373N Octal D-Type Transparent Latch—
$0.79
$0.28Product Information
Product Information
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Shipping & Returns
Description
These 8-bit registers feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. The high-impedance 3-state and increased high-logic-level drive provide these registers with the capability of being connected directly to and driving the bus lines in a bus-organized system without need for interface or pullup components. These devices are particularly attractive for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.
The eight latches of the 74S373N are transparent D-type latches, meaning that while the enable (C or CLK) input is high, the Q outputs follow the data (D) inputs. When C or CLK is taken low, the output is latched at the level of the data that was set up.
Schmitt-trigger buffered inputs at the enable/clock lines of the 74S373N devices simplify system design as ac and dc noise rejection is improved by typically 400 mV due to the input hysteresis. A buffered output-control (OC) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly.OC\ does not affect the internal operation of the latches or flip-flops. That is, the old data can be retained or new data can be entered, even while the outputs are off.
Features:
Choice of Eight Latches or Eight D-Type Flip-Flops in a Single Package
3-State Bus-Driving Outputs
Full Parallel Access for Loading
Buffered Control Inputs
Clock-Enable Input Has Hysteresis to Improve Noise Rejection
P-N-P Inputs Reduce DC Loading on Data Lines
20 pin DIP. Actual brand may vary from picture.
G12648
The eight latches of the 74S373N are transparent D-type latches, meaning that while the enable (C or CLK) input is high, the Q outputs follow the data (D) inputs. When C or CLK is taken low, the output is latched at the level of the data that was set up.
Schmitt-trigger buffered inputs at the enable/clock lines of the 74S373N devices simplify system design as ac and dc noise rejection is improved by typically 400 mV due to the input hysteresis. A buffered output-control (OC) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly.OC\ does not affect the internal operation of the latches or flip-flops. That is, the old data can be retained or new data can be entered, even while the outputs are off.
Features:
Choice of Eight Latches or Eight D-Type Flip-Flops in a Single Package
3-State Bus-Driving Outputs
Full Parallel Access for Loading
Buffered Control Inputs
Clock-Enable Input Has Hysteresis to Improve Noise Rejection
P-N-P Inputs Reduce DC Loading on Data Lines
20 pin DIP. Actual brand may vary from picture.
G12648
